Smart camera architecture based on embedded HW/SW co-processor

This paper describes an image acquisition and a processing system based on a new co-processor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the co-processor unit is integrated into the image acquisition loop. The acquisition and co-processing architecture is compatible with the majority of CMOS sensors. It enables the dynamic selection of a wide variety of acquisition modes (random region acquisition, variable image size, variable acquisition modes line/region based, multi-exposition image) as well as the reconfiguration or implementation of high-performance image pre-processing algorithms (calibration, filtering, de-noising, binarisation, pattern recognition). Furthermore, the processing and data transfer, from CMOS sensor to the processor, can be operated simultaneously to increase achievable performances. The co-processor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing (up to 8 successive pre-defined pre-processing stages), during the image acquisition process that can be defined according to each specific application requirement. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the performances. For instance the detection and reading of bar codes in the case of postal sorting applications, on a PC platform is limited to about 15 images (letters) per second. The new platform, beside being more compact, more flexible at the acquisition stage and easily installable in hostile environments can successfully acquire and fully process up to 50 image codes/s.